Standard cells are often specified to have a height that is an integer multiple of a minimum wiring pitch. This sizing makes a maximum number of wiring channels available for routing once the standard cells have been placed in a design. However, this sizing may provide more area in the standard cells than necessary to meet timing and/or power requirements. Furthermore, reductions in transistor size (e.g., fin-based field effect transistor (FINFET) spacing) may not optimally align with the minimum wiring pitch. Accordingly, maintaining standard cell height as an integer multiple of a minimum wiring pitch may result in a standard cell library that is oversized and consumes more power than necessary.